Chelsio Communications was formed in 2001 “to provide high-speed protocol-offload products to manufacturers of server, storage, and data-communications equipment.” In 2001, Chelsio received $11M in Series A funding, led by Sequoia. In 2002, NEA led a $19M Series B round. Other investors include Global Catalyst Partners, Horizon Ventures, and Pacesetter Capital. The company will seek additional capital later this year. Chelsio has 40 employees.
Chelsio is developing protocol acceleration technology. Featuring a highly scalable architecture, Chelsio has begun sampling its 10-Gigabit Ethernet adapter card with TCP offload engine in hardware, which delivers the low latency and superior throughput required for high-performance computing applications.
Chelsio’s 10-Gigabit Ethernet host-bus adapter technology recently broke through the 10s latency barrier for 10-Gigabit Ethernet. Chelsio claims to be the first 10G Ethernet adapter vendor delivering a TCP offload engine (TOE) in silicon and the first to deliver 10G iSCSI in silicon.
In a recent demo, Chelsio’s solution was shown transmitting standard 1500-Byte Ethernet frames in a peer-to-peer configuration at 7.8Gb throughput with less than 10 s latency from user to user and 50% CPU utilization with a 2.2GHz Opteron. The line-rate performance of the adapter stays consistent with equal and stable bandwidth per connection, whether there is one or 10,000 connections.
According to Chelsio, the best performance other 10GE adapters on the market can claim in transferring standard Ethernet frames is only 3 to 4Gbps, with higher latency and more than 100% CPU utilization in multi-Itanium-II processor systems. Chelsio’s 10G Ethernet adapter card simultaneously achieves high throughput, low latency and low CPU utilization – all while using the TCP/IP protocol suite with standard 1500-byte packets.
The T110 host bus adapter card is built with Chelsio’s Terminator ASIC, a deeply-pipelined VLIW architecture that delivers high-bandwidth and low-latency advantages over RISC-based multi-processor implementations. It is claimed to be the first chip on the market to include a 10G TOE. The chip is fabricated by TSMC on a 0.13u CMOS process.
The Terminator ASIC has a capacity of one million sessions, while the T110 card can support up to 64,000 connections.
The T110 & Terminator include pre-standard RDMA RDMA functionality and the product roadmap will include RDMA on chip. For low numbers of connections, Chelsion believes RDMA is not required to achieve low latency. For a lot of connections, RDMA will be required.
The T110 board is sampling now and is priced at $4,900 each in small quantities. Chelsio is an HBA company; however, if the opportunity for technology licensing of the Terminator chip makes sense, the company will do that as well.
Gartner estimates the total available market for 10G NICs in 2007 to be somewhere between $1.5B and $2B. The company will formerly introduce its products, roadmap and customers in September. Chelsio already has unnamed tier one OEM customers.
Competitors include Alacritech, NetEffect, Ammasso, Intel, andS2io. Competitive advantages include its ASIC development capability and the first claimed 10G TOE and iSCSCI in silicon.
Kianoosh Naghshineh, Founder, CEO and President (previously CEO and president of IP firm ASIC Designers)
Dr. Ásgeir Eiriksson, CTO (previously responsible for protocol design, ASIC chip design and implementation, and formal design methodology at Silicon Graphics)
Robert Miller, VP of Operations (previously VP of Operations for the Storage Solutions Group at Quantum)