PLsense was founded in February 2014 “to provide a unique and disruptive ultra-low power technology to increase IoT, mobile, wearable and other devices battery life by 4-5X. The company has raised $3.2M to date and is currently raising a Series B round of $5-10M. PLsense has 10 employees.
PLSense has developed an approach for IoT SoC design that achieves minimum energy operation for the targeted performance in a wide range of frequencies (up to 100MHz) dynamically required by the application. While achieving up to 90% energy reduction, as compared to the most advanced competitors, according to the company, PLSense designs are more reliable, provide better yield and have a longer lifetime.
Traditional designs use supply voltages in the range of 0.9V-1.8V to operate digital and analog circuits. While this design approach is fast and reliable, it dissipates excessive energy. PLSense uses low voltage operation in the “sub-threshold” or “near-threshold” regions to dramatically reduces energy dissipation. In sub/near-threshold designs, all transistors are operated from the supply voltage, which is below or near the transistor switching threshold voltage.
Sub/near threshold operation substantially reduces both leakage and switching (dynamic) energy dissipation, resulting in minimum energy dissipation. However, since sub/near threshold currents are much weaker than “super-threshold” currents, the time needed to change digital gate states is longer, which limits operating frequency.
Lower supply voltages also mean lower noise margins, reduced yield and increased vulnerability to process variations and temperature fluctuations. The characteristics of semiconductor behavior in sub/near-threshold are not well represented by standard transistors models and are different from those in super-threshold region, resulting in different sizing and ratio optimizations.
To overcome these challenges, PLSense provides a complete solution, combining a variety of patent-pending technologies at different abstraction levels, including physical, circuit, logic cells, architecture and software. PLSense significantly reduces the sensitivity of low voltage circuits to process and temperature variations and achieves minimum power dissipation for the targeted performance across the wide range of supply voltages without sacrificing reliability. PLSense solution includes a full set of digital libraries that are designed and optimized for low voltage operation and are fully compatible with standard manufacturing process and design tools.
The company’s first product is the PLS10, a general-purpose ultra-low power MCU, featuring support for DSP functions, DMA functionality and a broad range of interface options. The device utilizes the PLSense Near/Sub-threshold technology, including the Adaptive Dynamic Voltage Control (ADVC) mechanism, thus achieving a 3-7x power reduction compared with other MCUs with similar functionality.
The PLS10 architecture is based on the Synopsys ARC EM5D core with full DSP instruction set, which can be clocked at frequencies between 0.5 and 100MHz and achieves 1.8 DMIPS per MHz. PLsense selected the ARC EM5D core because its performance and energy per operation is much better than the ARM Cortex M4F, according to the company.
The device can be connected directly to a battery source (1.0 - 3.8V) and operates from internally-generated voltages between 0.45 and 1.1V. The device has 160K bytes of instruction memory, 32K bytes of data memory and 4K bytes of ROM for boot. Programs are stored in external serial flash. The company plans to integrate flash memory in the next product, the PLS20, which will be available next year.
Several companies offer MCUs and SoCs based on sub-threshold logic, including Ambic, PsiKick, and Minima – in this issue. PLsense argues that it supports real sub-threshold operation on a complete SoC at an advanced process node of 40nm. In addition, PLSense technology support Adaptive Dynamic Voltage Control (ADVC) that can adjust the operation voltage to the required speed and other environment conditions automatically. The company has a complete and comprehensive sub-threshold solution, comprised of different libraries, analog blocks, design flows and manufacturability / yield enhancements while working at the sub-threshold domain.
The PLS10 is fabricated by TSMC and is available now. PLS20 samples are targeted for Q2’17. Initial target applications include smart metering, smart alarm systems, wearable devices, and medical personal devices.
Dr. Isaac Shenberg, Chairman (key contributor to growing Zoran from a start through IPO, secondary to >$350M/year revenue and merger with CSR. Also held Senior VP roles at CSR, Zoran, and Rafael)
Uzi Zangi, CEO & Co-Founder (previously held executive roles at Zoran and Siverge Networks)
Neil Feldman, COO & Co-Founder (previously VP of Hardware and RF for Siano Mobile Silicon, and Senior Manager of the analog team at Zoran)
Hadar Tal, VP of Sales & Business Development and Co-Founder (previously VP of Worldwide Sales at Siverge Networks)
Professor Alexander Fish, Technical Advisor (Associate Professor of Engineering at Bar Ilan University and head of the Nanoelectronics track. 15+ years of research experience in the area of low power IC design)