RISC-V inventors Krste Asanovic, Yunsup Lee and Andrew Waterman founded SiFive in July 2015 as the first fabless semiconductor company to build customized silicon based on the free and open RISC-V instruction set architecture (ISA). Sutter Hill Ventures has provided funding. The company has 20 employees and is growing rapidly.
SiFive recently unveiled its flagship Freedom family of SoC platforms. Built around the RISC-V ISA invented by the company’s founders at the University of California, Berkeley, the Freedom U500 and Freedom E300 platforms represent a new approach to designing and producing SoCs that redefines traditional silicon business models and reverses prohibitively rising licensing, design and implementation costs.
RISC-V is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley. At the 4th RISC-V workshop that took place in July 2016 in Boston, more then 40 member companies, including significant industry heavyweights like Google, Microsoft, IBM, NVIDIA, Qualcomm, HP Enterprise, AMD, Western Digital, Oracle, attended.
RISC-V is a completely open ISA that is freely available to academia and industry. It is a real ISA suitable for direct native hardware implementation, not just simulation or binary translation. The small base integer ISA is usable as a base for customized accelerators, while optional standard extensions support general-purpose software development.
It supports extensive user-level ISA extensions and specialized variants, including 32-bit, 64-bit, and 128-bit address space variants. It also supports highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors. It is fully virtualizable to ease hypervisor development. Optional variable-length instructions expand the available instruction encoding space and support optional dense instruction encoding for improved performance, static code size, and energy efficiency.
RISC-V was born to address the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures. SiFive’s hardware designs leverage software and tools available from the open-source community under the guidance of the RISC-V Foundation, dramatically reducing the cost of developing custom silicon. System designers can use the SiFive Freedom platforms to focus on their own differentiated processor without having the overhead of developing a modern SoC, fabric or software infrastructure.
Developed in lockstep with the RISC-V standard, SiFive’s Coreplex IP is designed for ASIC, FPGA, and other implementations. The Coreplex U Series and E Series span from high-performance 64-bit RISC-V multicore Unix-capable processors to 32-bit RISC-V embedded microcontrollers, and are customizable and extensible.
The Freedom platforms comprise a complete software specification, board OS support packages (BSPs), development boards and base silicon. The platforms provide customers with the ability to create their own silicon enhancements and customizations, which SiFive then quickly incorporates and delivers to the customer at a much lower cost and faster time-to-market than traditional custom silicon designs. The platforms also provide significant performance and power advantages over existing microcontrollers and FPGAs, according to the company.
The Freedom Unleashed (U) family features a series of customizable Linux-capable SoC platforms, based on SiFive’s U5 Coreplex, the most advanced multicore RISC-V CPUs, running at 1.6 GHz or higher with support for accelerators and cache coherency. Designed in TSMC 28nm, the first member of the Freedom U family, the U500 platform, targets customers in markets such as machine learning, storage, and networking. The platform also supports standard high-speed peripherals including PCIe 3.0, USB 3.0, Gigabit Ethernet, and DDR3/DDR4.
The Freedom Everywhere (E) family features a series of customizable microcontroller SoC platforms, based on SiFive’s E3 Coreplex, the most efficient RISC-V CPU with support for RISC-V compressed instructions, which have been shown to reduce code size by up to 30%. The SiFive E3 Coreplex is designed in TSMC 180nm and architected to have minimal area and power. The E300 platform, the first member of the Freedom Everywhere family, is designed for embedded microcontrollers, IoT, and wearable markets.
The Freedom Unleashed and Freedom Everywhere platforms are available now in full FPGA models. Developers can prototype their customizations in the form of custom RISC-V instructions, accelerators and co-processors. SiFive offers several development kits, incorporating both Microsemi and Xilinx FPGAs. Microsemi is a member of the RISC-V foundation and an early customer of SiFive.
SiFive believes its Freedom family of SoC platforms is the first commercially available open source-enabled semiconductors on the market. The company believes its platforms will provide access to companies who wouldn’t normally have access to custom chips, due to ever increasing investment required for traditional chipmakers to design custom silicon.
SiFive works with customers to deliver customized silicon based on the RISC-V architecture. Ultimately, SiFive delivers chips through a fabless business model. The company is in talks with a number of companies regarding their interest in the Freedom Unleashed and Freedom Everywhere platforms.
Stefan Dyckerhoff, CEO (also Managing Director at Sutter Hill Ventures. Previously EVP of the Platform Systems Division at Juniper Networks)
Yunsup Lee, Ph.D., Co-Founder & CTO (previously co-designed the RISC-V ISA and the first RISC-V microprocessors with Andrew Waterman at UC Berkeley, and led the development of the Hwacha decoupled vector-fetch extension)
Professor Krste Asanovic, Ph.D., Co-Founder & Chief Architect (Professor in the EECS Department at the University of California, Berkeley, where he is Director of the ASPIRE Lab. He leads the RISC-V ISA project at Berkeley, and is Chairman of the RISC-V Foundation.)
Andrew Waterman, Ph.D., Co-Founder & Chief Engineer (Co-designed the RISC-V ISA and the first RISC-V microprocessors with Yunsup Lee at UC Berkeley)
Jack Kang, VP of Product and Business Development (previously held senior business development, product management, and product marketing roles at NVIDIA and Marvell)
Han Chen, Chief Engineer (previously Principal Methodologist at ARM and taped out multiple chips at Synopsys)