efabless was founded in April 2014 to develop an open innovation, hardware creation platform for the creation of “smart” products. efabless applies the concepts of crowdsourcing and open community innovation to key aspects of IC development and commercialization. The company has raised $2M from angels, including Jack Hughes, funder of Top-coder, Lucio Lanza (LanzaTechVentures) and Mike Wishart, and is currently seeking $3M in Series A financing. efabless has 8 employees.
efabless is a marketplace that connects a global community of designers with a global community of customers. Specializing in the design of analog/mixed-signal IP and ICs, MEMS, and agile ASICs, efabless gives designers the means to define, develop and monetize their work. Its community spans approximately 1,000 members from 30 countries around the world. As examples, foundry customers post design requests at efabless to fill gaps in their IP portfolio for process nodes and IC customers request custom analog and digital IP for new designs.
efabless gives chip companies two ways to obtain analog & mixed-signal IP: search for existing IP in its growing library of verified designs or request the efabless community to design new IP and derivatives. The efabless platform allows its customers and community to formulate, communicate and agree on design requirements, quantitatively evaluate the successful completion of the resulting design specifications and deliver prototypes. Over time, the marketplace will offer a wide variety of customizable reference designs.
IP protection is clearly a concern with this business model. Efabless addresses IP protection with a three-prong model that uses community methods to ensure “clean” IP creation, hides critical foundry IP, and uses black boxes to protect designers’ IP.
The company works with customers to organize design challenges that yield the required design deliverables needed for IP integration. Requirements are solidified in the form of a data sheet, along with a budget, schedule and performance criteria. The project is then partitioned into key building blocks to be designed by the members of the efabless community. Multiple design teams can compete to meet the specifications. At each stage, design deliverables are verified against the spec, using an automated characterization engine, ensuring that customers only pay for verified design outcomes. Customers ultimately choose the design that best meets their requirements.
efabless provides a full path from open IP to silicon products. The platform has three main pillars:
- a github-like openness for the design of IP with specific focus on analog / mixed-signal IP,
- a complete foundry-supported design toolset,
- a customer-focused marketplace for community-developed hard IP.
efabless has developed a complete set of design software including system design, schematic entry, spice simulation, layout editing, DRC, LVS and parasitic extraction, as well as a complete RTL-to-GDS digital design flow that includes synthesis, STA, placement and routing. Community members retain the rights to their IP ownership. However, to enable the ability to design with foundry PDKs without requiring NDAs, the IP is not available for downloading from the system. IP is segmented so that each individual involved with a design sees only those specifications and design files necessary to complete their job. The rest of the design is a “black box” represented by simulation models and vectors.
efabless and X-FAB launched the first design challenge to deliver an IP block for an ultra-low power voltage reference using X-FAB’s 350nm (XH035) low noise mixed-signal process. Entrants used the efabless online platform for everything needed to design, verify and deliver the IP, including process technology information, design software, a foundry process design kit (PDK) and a variety of technical guides and webinars.
88 engineers from 26 countries accepted the challenge, and multiple designs were completed on time in conformance with the X-FAB spec. The first, second and third place winners were awarded cash prizes of $7000, $5000 and $3000, respectively, and will earn licensing revenues from the use of their IP through efabless’ online marketplace and X-FAB’s IP Portal. Good circuits that do not win the contest are also added to the MarketPlace.
Compared to other marketplaces for IP, at efabless, customers can search for IP modules and request derivatives and new IP, including IP to be designed by the efabless community. “Try before buying” allows customers to integrate IP in a design and simulate it before licensing.
efabless also offers on-line lab-based learning to its community. The fist offering is CMOS Analog Circuit Design, authored by Professor Phillip Allen, Professor Emeritus at Georgia Tech and co-author of the textbook “CMOS Analog Circuit Design”. The efabless roadmap includes full chip assembly as well as system-level hardware solutions. efabless offers community members and customers access to shuttles. The company is designing an open source HW platform board to enable characterization of community IP. The company also plans to forge partnerships with labs and test facilities that support low volume production.
Michael Wishart, CEO (previously Chairman, Technology Group, Investment Banking Division at Goldman Sachs, currently member of the Board of Directors at Cypress)
Mohamed Kassem, Founder & CTO (previously OMAP Business Manager and Head, Advanced Analog IP Engineering at TI)
Rajeev Srivastava, VP of Platform Engineering (previously founder, President & CEO of Silverline DA, which was acquired by efabless)
Bertrand Irissou, Head of Operations (previously Director of Marketing, Analog Business at Microsemi and founder and CEO of ASIC Advantage)
Tim Edwards, Ph.D., SVP of Analog & Platform (previously a design engineer at Analog Devices and host of Open Circuit Design)
Greg Shaurette, SVP of Web and IT (previously with Wells Fargo, Department of Public Health, SF, and Kaiser)