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Dover Microsystems -- Secure Processor IP  
Founded: Jul 2018
Status: Private
Source: Semiconductor Times, 08/18
203 Crescent Street, Suite 108
Waltham, MA 02453

Dover Microsystems was founded in July 2017 based on more than eight years of R&D and $31M of investment ďto bring real security, privacy, and safety enforcement to silicon.Ē In February 2018, the company secured $6 million in seed funding led by Hyperplane Venture Capital and including Draper, Qualcomm Ventures, and the Hub Angels Investment Group. Dover is currently engaged in raising a $10M - $20M Series A round. The company has 18 full-time employees.

The majority of cyberattacks exploit bugs in software and on average there are 15 bugs per thousand lines of code. Conventional processors blindly execute instructions, even if those instructions were exploited or are unsafe. Processors donít know the difference between good and bad instructions, and they canít enforce what they donít know.

In June 2010, while at BAE Systems, Greg Sullivan and Jothy Rosenberg won their proposal for the DARPA CRASH (Clean-Slate Design of Resilient, Adaptive, Secure Hosts) SAFE program to research and develop a clean-slate computer architecture optimized for security. In June 2015, at the conclusion of the DARPA research project, Draper President Ken Gabriel (former DARPA Deputy Director) invited Jothy, Greg, and team to incubate and commercialize their technology at Draper. Draper has maintained a minority equity stake in Dover and has a licensed partnership to serve its traditional government and military customers with the technology developed by the Dover team.

By solving security at the silicon level, Doverís CoreGuard solution protects computing systems from vulnerabilities caused by human error during software development. Based on research conducted as part of the DARPA funded CRASH SAFE program, CoreGuard has demonstrated immunity to entire classes of cyberattack, including buffer overflow, code injection, and privilege escalation attacks. Systems utilizing CoreGuard are protected from name brand attacks like Heartbleed and Wannacry and can even be protected from zero-day attacks.

CoreGuard monitors every instruction a host processor executes to ensure it complies with a set of security, safety, and privacy rules called micropolicies. If an instruction violates an existing micropolicy, CoreGuard stops it from executing before any damage can be done. Micropolicies are designed to stop entire classes of attacks, including buffer overflows, code injection, data exfiltration, and even safety violations.

MITREís Common Weakness Enumeration (CWE) list divides 705 known vulnerabilities into seven classes, and CoreGuard micropolicies are designed to stop these classes of attacks. Because of this, CoreGuard can block malicious behaviors from known and unknown sources and can defend against zero-day attacks that exploit a software vulnerability unknown to the software maker or user.

CoreGuard can be implemented with any RISC processor and is currently optimized for the latest generation RISC-V architecture. CoreGuard currently does not support CISC processors. It is optimized for embedded and industrial IoT devices with smaller software stacks. CoreGuard supports FreeRTOS version 10. Support for additional RTOSs is in process, and a Linux solution will be offered in a future release.

Hardware-based security solutions include Arm TrustZone and Intel SGX, which enhance security by using compartmentalization. This approach may limit an attacker's impact; however, it cannot stop an attacker from gaining access to a compartment by exploiting software vulnerabilities. Dover argues that CoreGuard is only cybersecurity solution specifically designed to stop the attackerís ability to take over the processor.

NXP will utilize Doverís CoreGuard technology to create inherently secure processors for embedded devices. This technology will complement the strong security foundation implemented in NXP processors, which already include functions such as secure boot, crypto acceleration, and tamper resistance.

The company is engaged with some of the biggest names in the semiconductor industry, as well as several major EDA vendors. Additionally, Dover is actively speaking with IoT device manufacturers that are interested in acquiring its technology through their suppliers.

Jothy Rosenberg, Ph.D., Co-Founder and CEO (previously founded MasPar, Novasoft, Webspective, GeoTrust, Service Integrity, Ambric, Mogility, and Aguru)

Steven Milburn, CTO (previously an SOC Architect at Microchip)

Gary Christelis, Chief Revenue Officer (previously an international corporate lawyer at Baker & McKenzie and Bingham McCutchen, President and CEO of GET Group and co-founder of Stratevise)

Marco Ciaffi, Co-Founder & VP of Engineering (previously Senior Engineering Manager at RSA Security)

Greg Sullivan, Ph.D., Chief Scientist (previously held software engineering roles and academic posts at MIT and Boston College)

Dan Ganousis, Director of Sales (most recently a business development consultant for embedded processor IP vendors Codasip, Cortus, and Andes)

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